This invention applies to the field of 3D Thin Die Packaging or multiple thin IC dies packaging in semiconductor industry. In currently applied processes and corresponding devices assembly of thin dies is typically performed by welding and/or gluing layers and/or by wire bonding.
In a typical wire bonding process wires are bonded to the stacked dies in order to provide electrical connectivity. The wire bonding process is time consuming, relatively complex, and enables only a limited wiring density between the dies. Furthermore, the wire bonding process results in a structure having an essentially “pyramidal” shape, which reduces the useful area of the dies.
Stacking of multiple dies normally requires high alignment accuracy. Currently the positioning of the dies is accomplished by equipment that is not capable of achieving such high alignment accuracy (typically the alignment error is of an order of magnitude of about 5 μm or more).
In US 2004/0238933 A1 a packaging method for packaging electronic elements is disclosed. The method comprises the provision of a plurality of stud bumps on a substrate by means of a stud bump process to align with a plurality of vias of a stack of electronic elements. The stud bumps respectively pass through the vias and electrically connect the electronic elements, thereby creating multiple levels of substrates aligned by the same stud bumps.
This process and the corresponding device have the disadvantage that the alignment is accomplished for the entire stack of elements and depends on the positions of the stud bumps provided on the substrate. Therefore the known process and device do not allow for different alignment of the electronic elements at the respective levels of elements. On top of that, the pitch between the vertical interconnects is limited by the deformation of the bumps at the base substrate, in practice the bump is deformed by several tens of μm overall, there fore limiting the pitch to more than 50 μm.
In U.S. Pat. No. 6,577,013 B1 a chip-size semiconductor package (“CSP”) containing stacked dies is disclosed. The dies are mounted on one another in a stack such that corresponding ones of vias provided in respective dies are aligned. An electrically conductive wire or pin is present in each set of aligned vias and soldered to corresponding ones of the terminal pads. Therefore the CSP disclosed in this document does not allow for an individual alignment of the dies at the respective levels.
In US 2006/0012055 A1 a method of fabricating a semiconductor device is disclosed. The semiconductor device comprises a semiconductor die provided with a plurality of ball bumps, each ball bump having a base portion and a protruding portion. A lead frame is attached to the semiconductor die by placing openings in the frame, that have been provided at positions corresponding to those of the ball bumps, over the protruding portions of the ball bumps and subsequently coining the protruding portion of the ball bump, for instance by a coining tool bit, to form a rivet which provides for bonding and securing the lead frame to the semiconductor die. Instead of coining (pressing) the ball bumps they may be heated. This causes the upper part of the ball bumps to melt and to wet the lead frame such that upon cooling the bumps provide for riveting of the lead frame. The ball bumps are either solder bumps or formed by electroplating fabrication and may for instance be made of gold or a gold alloy.
A disadvantage of this method is that the bump process is that it has a narrow process window. Furthermore, placement of the ball bumps is not very accurate.
Another disadvantage of the known method is that in case of stacking multiple dies, the pressure exerted on the dies when a further die is placed on top of a previous one, may have a damaging effect on the dies, especially when the dies are very thin.